1. Technical Field
The present disclosure relates to a semiconductor device. In particular, the present disclosure relates to a semiconductor device having integrated passive components.
2. Description of the Related Art
A three-dimensional (3D) inductor structure (e.g., formed through multiple layers of a multi-layer structure) may be formed on a semiconductor substrate, and may be surrounded by a passivation layer. Quality of the 3D inductor structure may be related to a height thereof. In some implementations, a relatively tall 3D inductor structure may be desirable; however, height of the 3D inductor structure is constrained by the passivation layer. Additionally, greater height of the 3D inductor structure and greater thickness of the passivation layer (e.g., to accommodate a 3D inductor structure of greater height) also result in higher cost.